High speed digital telecommunications switches may comprise many interconnected integrated circuit (IC) chips. Chip-to-chip communication is achieved by transceivers, i.e. drivers and receivers, which transmit and receive signals along transmission lines interconnecting the integrated circuit chips. The demand for higher circuit speeds, higher chip-to-chip bit rates, and lower on-chip power consumption places corresponding demands the output drivers/input buffers of the transceivers. Low power consumption is essential to allow system designers to increase the number of I/Os per chip while maintaining high reliability and keeping the total power dissipation within thermal limits.
Bipolar circuits such as ECL (emitter coupled logic) or CML (current mode logic) can meet the speed requirements. ECL is conventionally used for maximum speed, while CML is used for lower power consumption. However, both CML and ECL, when used as drivers, consume large amounts of power, particularly for level shifting/buffering of the input signals, and for the current switch (the tail current). Thus low power consumption is an major concern as the number of I/Os for telecommunications integrated circuits increases.
Various dynamic circuits techniques to reduce power consumption of ECL/CML logic circuits, while maintaining or increasing their speeds, have been reported. However these techniques were intended for bipolar VLSI logic applications, and are not suitable for ECL/CML output driver applications.
Recently many low voltage swing driver circuits have been reported. These circuits range from reduced swing CMOS, CMOS pseudo ECL, or CMOS 100K ECL, and CMOS GTL. CMOS reduced swing transceivers have limited speed. CMOS pseudo ECL or CMOS 100K ECL are complicated and have higher power consumption. For example, CMOS GTL bi-directional transceiver is described in U.S. Pat. No. 5,023,488 to Gunning, entitled "Drivers and receivers for interfacing VLSI CMOS circuits to transmission lines" and requires different reference and termination voltages. Another transceiver having reduced EMI and power dissipation is described in copending U.S. patent application Ser. No. 08/368,945 filed Jan. 5, 1995 to Sasaki et al. entitled "Signal transmitter and transceiver and apparatus incorporating the same". However these receivers, as well as true or pseudo Bipolar ECL or CML transceivers, each require different termination voltages.
Thus, existing low voltage swing transceiver circuits are incompatible with each other due to their different termination/reference voltage requirements. In systems using parts with different transceiver types, signal conversion or interface circuitry, as well as multiple termination and reference voltages are required, which adds to the overall cost and complexity of the system.
Moreover, the Digital Signal Processing (DSP) portions of high speed communications chips are usually implemented using CMOS logic. As future submicron and deep submicron Bipolar CMOS technologies, are scaled down, the supply voltages will be scaled down, to maintain reliability of short channel MOS devices. Since BiCMOS technology combining bipolar and CMOS (complementary metal oxide semiconductor) technology has proven to be an excellent workhorse for telecommunications applications, there is a need for BiCMOS compatible transceivers capable of meeting the requirements mentioned above for high speed chip-to-chip communications.